Interconnect testing has drawn renewed attention recently due to the development of interposer-based 2.5-D (two-and-half-dimensional) stacked integrated circuits and through-silicon-via (TSV) based 3-D (three-dimensional) stacked integrated circuits. In these types of integrated circuits, multiple dies are bonded together through interconnects going through chips to reduce power consumption and to increase bandwidth and integration. The interconnect fabrication mechanisms can lead to not only catastrophic defects but also parametric defects. It is thus necessary to test interconnects thoroughly.
Recently, test methods for TSVs either in the pre-bond stage or in the post-bond stage have been proposed. Some of them target functional faults such as stuck-at faults or completely open faults, while some other methods can also detect parametric faults such as resistive open faults or leakage faults. To perform some of these methods, analog circuitry is required in the design-for-circuit (DFT) circuit. In general, a method for testing TSVs can be employed to test interposer wires after some modification.
For high-speed interconnect test, one needs to control the so-called “launch-to-capture timing interval” (i.e., the timing interval between the time when a test stimulus is launched at a pitcher cell and the time when a capture cell latches the result). In a method disclosed in Wang et al, “Post-bond testing of the silicon interposer and micro-bump C4 interconnects for Si-carrier SOP applications,” Proc. of IEEE Asian Test Symp., pp. 147-152, 2013 (referred to as Wang hereinafter), double pulses are needed (similar to the one used in a launch-off-capture type of at-speed logic test). The timing signals for the pitcher cell and the catcher cell have to be separated so that the transition is launched at an edge of one pulse and captured at an edge of the other pulse. If the timing signals of the pitcher and the catcher cells are synchronized, then the launch-to-capture interval equals the timing difference between the double pulses (which is usually the functional clock cycle time). However, the timing signals could arrive at the pitcher cell (in a specific die) to the catcher cell (in another die) at different times. If the timing difference is taken into account, then, the launch-to-capture timing interval could be different from what has been anticipated. This problem is referred to as across-die timing skew problem.
The synchronous method disclosed in Wang may be employed to resolve the problem. This method is to assume that the timing signals at the pitcher and catcher cells are already synchronized (which is true when every interconnect is connecting a functional flip-flop to a functional flip-flop), or clock synchronization techniques are particularly invoked to remove the timing skew problem. A drawback for the synchronization method is that it needs an extra clock synchronization tree for a large number of pitcher and catcher cells scattering multiple dies.
Another method free of the across-die timing skew problem was disclosed in Lin et al., “Small Delay Testing for TSVs in 3D ICs,” IEEE Proc. of Design Automation Conf., June 2012. It uses a variable-output-threshold (VOT) technique to enhance a conventional oscillation test method. In this method, two oscillation signals are produced, with their difference reflecting the delay of the TSV under test. After post-processing, a TSV with a delay fault can be identified. This method was enhanced by a wire-length normalization technique, disclosed in Huang et al., “Delay Testing and Characterization of Post-Bond Interposer Wires in 2.5-D ICs”, Proc. of Int'l Test Conf. (ITC), September 2013, to make it further suitable for interposer wires of diverse wire lengths. Even though these methods are effective for detecting parametric faults, post-processing of the measurement data (such as outlier analysis) may be needed to perform fault detection and/or diagnosis.
Due to the limitations of these current methods, it is desirable to develop a new method that does not require a cross-die zero-skew clock signal, sophisticated post-processing, or analog-based test circuitry.